hwClockSrcCfgPhyState 1.3.6.1.4.1.2011.5.25.186.1.11.1.22

The PHY clock state of ports.

Informations

Access Type
readonly cardTypeNotSupport(0), slave(1), master(2), speedNotSupport(3), portDown(4)

Parent

1.3.6.1.4.1.2011.5.25.186.1.11.1 hwClockSrcCfgEntry